Xilinx Design Summary

VGA Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	1,280	15,360	8%
Number of 4 input LUTs	2,149	15,360	13%
Logic Distribution
Number of occupied Slices	1,901	7,680	24%
Number of Slices containing only related logic	1,901	1,901	100%
Number of Slices containing unrelated logic	0	1,901	0%
Total Number of 4 input LUTs	2,811	15,360	18%
Number used as logic	2,149
Number used as a route-thru	138
Number used for Dual Port RAMs	524
Number of bonded IOBs	113	173	65%
IOB Flip Flops	20
Number of Block RAMs	13	24	54%
Number of MULT18X18s	5	24	20%
Number of GCLKs	4	8	50%
Number of RPM macros	4
Total equivalent gate count for design	933,094
Additional JTAG gate count for IOBs	5,424

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met