| VGA Project Status | |||
| Project File: | vga.ise | Current State: | Placed and Routed |
| Module Name: | vga |
|
No Errors |
| Target Device: | xc3s200-5ft256 |
|
8 Warnings |
| Product Version: | ISE 9.1.03i |
|
Mon Dec 10 21:25:35 2007 |
| VGA Partition Summary | |||
| No partition information was found. |
| Device Utilization Summary | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops | 58 | 3,840 | 1% | |
| Number of 4 input LUTs | 188 | 3,840 | 4% | |
| Logic Distribution | ||||
| Number of occupied Slices | 113 | 1,920 | 5% | |
| Number of Slices containing only related logic | 113 | 113 | 100% | |
| Number of Slices containing unrelated logic | 0 | 113 | 0% | |
| Total Number of 4 input LUTs | 212 | 3,840 | 5% | |
| Number used as logic | 188 | |||
| Number used as a route-thru | 12 | |||
| Number used for Dual Port RAMs | 12 | |||
| Number of bonded IOBs | 40 | 173 | 23% | |
| IOB Flip Flops | 6 | |||
| Number of Block RAMs | 6 | 12 | 50% | |
| Number of MULT18X18s | 1 | 12 | 8% | |
| Number of GCLKs | 1 | 8 | 12% | |
| Total equivalent gate count for design | 399,849 | |||
| Additional JTAG gate count for IOBs | 1,920 | |||
| Performance Summary | |||
| Final Timing Score: | 0 | Pinout Data: | Pinout Report |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
| Timing Constraints: | All Constraints Met | ||
| Detailed Reports | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | Current | Sat Dec 8 18:11:49 2007 | 0 | 5 Warnings | 1 Info |
| Translation Report | Current | Sat Dec 8 18:11:59 2007 | 0 | 1 Warning | 0 |
| Map Report | Current | Sat Dec 8 18:12:09 2007 | 0 | 2 Warnings | 3 Infos |
| Place and Route Report | Current | Sat Dec 8 18:12:25 2007 | 0 | 0 | 2 Infos |
| Static Timing Report | Current | Sat Dec 8 18:12:30 2007 | 0 | 0 | 3 Infos |
| Bitgen Report | |||||