Timing Report

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Design Name ethernutcpld
Device, Speed (SpeedFile Version) XC9536, -5 (3.0)
Date Created Thu Jan 15 19:52:48 2009
Created By Timing Report Generator: version J.33
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Pad to Pad Delay (tPD) 9.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
TS1004 0.0 0.0 0 0
TS1005 0.0 0.0 0 0
TS1006 0.0 0.0 0 0
TS1007 0.0 0.0 0 0
TS1008 0.0 0.0 0 0
TS1009 0.0 0.0 0 0
TS1010 0.0 0.0 0 0
TS1011 0.0 0.0 0 0
TS1012 0.0 0.0 0 0
AUTO_TS_F2F 0.0 0.0 0 0
AUTO_TS_P2P 0.0 9.0 88 88
AUTO_TS_P2F 0.0 0.0 0 0
AUTO_TS_F2P 0.0 0.0 0 0


Constraint: TS1000

Description: PERIOD:PERIOD_adx_7.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_adx_6.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_adx_5.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_adx_4.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1004

Description: PERIOD:PERIOD_adx_3.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1005

Description: PERIOD:PERIOD_adx_2.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1006

Description: PERIOD:PERIOD_adx_1.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1007

Description: PERIOD:PERIOD_adx_0.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1008

Description: PERIOD:PERIOD_bank<4>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1009

Description: PERIOD:PERIOD_bank<3>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1010

Description: PERIOD:PERIOD_bank<2>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1011

Description: PERIOD:PERIOD_bank<1>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1012

Description: PERIOD:PERIOD_bank<0>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
a<0> to ad<0> 0.000 9.000 -9.000
a<0> to ad<1> 0.000 9.000 -9.000
a<0> to ad<2> 0.000 9.000 -9.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)



Number of constraints not met: 1

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason

Setup/Hold Times for Clocks


Clock to Pad Timing


Clock to Setup Times for Clocks


Pad to Pad List

Source Pad Destination Pad Delay
a<0> ad<0> 9.000
a<0> ad<1> 9.000
a<0> ad<2> 9.000
a<0> ad<3> 9.000
a<0> ad<4> 9.000
a<0> ad<5> 9.000
a<0> ad<6> 9.000
a<0> ad<7> 9.000
a<1> ad<0> 9.000
a<1> ad<1> 9.000
a<1> ad<2> 9.000
a<1> ad<3> 9.000
a<1> ad<4> 9.000
a<1> ad<5> 9.000
a<1> ad<6> 9.000
a<1> ad<7> 9.000
a<2> ad<0> 9.000
a<2> ad<1> 9.000
a<2> ad<2> 9.000
a<2> ad<3> 9.000
a<2> ad<4> 9.000
a<2> ad<5> 9.000
a<2> ad<6> 9.000
a<2> ad<7> 9.000
a<3> ad<0> 9.000
a<3> ad<1> 9.000
a<3> ad<2> 9.000
a<3> ad<3> 9.000
a<3> ad<4> 9.000
a<3> ad<5> 9.000
a<3> ad<6> 9.000
a<3> ad<7> 9.000
a<4> ad<0> 9.000
a<4> ad<1> 9.000
a<4> ad<2> 9.000
a<4> ad<3> 9.000
a<4> ad<4> 9.000
a<4> ad<5> 9.000
a<4> ad<6> 9.000
a<4> ad<7> 9.000
a<5> ad<0> 9.000
a<5> ad<1> 9.000
a<5> ad<2> 9.000
a<5> ad<3> 9.000
a<5> ad<4> 9.000
a<5> ad<5> 9.000
a<5> ad<6> 9.000
a<5> ad<7> 9.000
a<6> ad<0> 9.000
a<6> ad<1> 9.000
a<6> ad<2> 9.000
a<6> ad<3> 9.000
a<6> ad<4> 9.000
a<6> ad<5> 9.000
a<6> ad<6> 9.000
a<6> ad<7> 9.000
a<7> ad<0> 9.000
a<7> ad<1> 9.000
a<7> ad<2> 9.000
a<7> ad<3> 9.000
a<7> ad<4> 9.000
a<7> ad<5> 9.000
a<7> ad<6> 9.000
a<7> ad<7> 9.000
rd_n ad<0> 9.000
rd_n ad<1> 9.000
rd_n ad<2> 9.000
rd_n ad<3> 9.000
rd_n ad<4> 9.000
rd_n ad<5> 9.000
rd_n ad<6> 9.000
rd_n ad<7> 9.000
a<0> nic_cs_n 5.000
a<1> nic_cs_n 5.000
a<2> nic_cs_n 5.000
a<3> nic_cs_n 5.000
a<4> nic_cs_n 5.000
a<5> nic_cs_n 5.000
a<6> nic_cs_n 5.000
a<6> sa<0> 5.000
a<6> sramcs_n 5.000
a<7> nic_cs_n 5.000
a<7> sa<0> 5.000
a<7> sa<1> 5.000
a<7> sa<2> 5.000
a<7> sa<3> 5.000
a<7> sa<4> 5.000
a<7> sramcs_n 5.000



Number of paths analyzed: 88
Number of Timing errors: 88
Analysis Completed: Thu Jan 15 19:52:48 2009