cpldfit: version J.33 Xilinx Inc. Fitter Report Design Name: ethernutcpld Date: 1-15-2009, 7:52PM Device Used: XC9536-5-VQ44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 23 /36 ( 64%) 42 /180 ( 23%) 34 /72 ( 47%) 13 /36 ( 36%) 34 /34 (100%) ** Function Block Resources ** Function Mcells FB Inps Signals Pterms IO Block Used/Tot Used/Tot Used Used/Tot Used/Tot FB1 9/18 16/36 16 13/90 9/17 FB2 14/18 18/36 18 29/90 14/17 ----- ----- ----- ----- 23/36 34/72 42/180 23/34 * - Resource is exhausted ** Global Control Resources ** Global clock net(s) unused. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 11 11 | I/O : 28 28 Output : 15 15 | GCK/IO : 3 3 Bidirectional : 8 8 | GTS/IO : 2 2 GCK : 0 0 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 34 34 ** Power Data ** There are 23 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 23 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State nic_cs_n 1 8 FB1_6 2 I/O O STD FAST sramcs_n 1 2 FB1_10 6 I/O O STD FAST sa<4> 1 2 FB1_11 7 I/O O STD FAST sa<3> 1 2 FB1_12 8 I/O O STD FAST sa<2> 1 2 FB1_13 12 I/O O STD FAST adx<6> 2 2 FB1_14 13 I/O O STD FAST RESET adx<7> 2 2 FB1_15 14 I/O O STD FAST RESET adx<4> 2 2 FB1_16 16 I/O O STD FAST RESET adx<5> 2 2 FB1_17 18 I/O O STD FAST RESET sa<0> 2 3 FB2_3 36 GTS/I/O O STD FAST sa<1> 1 2 FB2_5 34 GTS/I/O O STD FAST ad<6> 1 9 FB2_6 33 GSR/I/O I/O STD FAST ad<7> 1 9 FB2_7 32 I/O I/O STD FAST ad<4> 3 11 FB2_8 31 I/O I/O STD FAST RESET ad<5> 1 9 FB2_9 30 I/O I/O STD FAST ad<2> 3 11 FB2_10 29 I/O I/O STD FAST RESET ad<3> 3 11 FB2_11 28 I/O I/O STD FAST RESET ad<0> 3 11 FB2_12 27 I/O I/O STD FAST RESET ad<1> 3 11 FB2_13 23 I/O I/O STD FAST RESET adx<1> 2 2 FB2_14 22 I/O O STD FAST RESET adx<0> 2 2 FB2_15 21 I/O O STD FAST RESET adx<3> 2 2 FB2_16 20 I/O O STD FAST RESET adx<2> 2 2 FB2_17 19 I/O O STD FAST RESET ** 11 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use a<3> FB1_1 40 I/O I a<4> FB1_2 41 I/O I a<6> FB1_3 43 GCK/I/O I a<5> FB1_4 42 I/O I a<7> FB1_5 44 GCK/I/O I ale FB1_7 1 GCK/I/O I rd_n FB1_8 3 I/O I wd_n FB1_9 5 I/O I a<2> FB2_1 39 I/O I a<1> FB2_2 38 I/O I a<0> FB2_4 37 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 16/20 Number of signals used by logic mapping into function block: 16 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 40 I/O I (unused) 0 0 0 5 FB1_2 41 I/O I (unused) 0 0 0 5 FB1_3 43 GCK/I/O I (unused) 0 0 0 5 FB1_4 42 I/O I (unused) 0 0 0 5 FB1_5 44 GCK/I/O I nic_cs_n 1 0 0 4 FB1_6 2 I/O O (unused) 0 0 0 5 FB1_7 1 GCK/I/O I (unused) 0 0 0 5 FB1_8 3 I/O I (unused) 0 0 0 5 FB1_9 5 I/O I sramcs_n 1 0 0 4 FB1_10 6 I/O O sa<4> 1 0 0 4 FB1_11 7 I/O O sa<3> 1 0 0 4 FB1_12 8 I/O O sa<2> 1 0 0 4 FB1_13 12 I/O O adx<6> 2 0 0 3 FB1_14 13 I/O O adx<7> 2 0 0 3 FB1_15 14 I/O O adx<4> 2 0 0 3 FB1_16 16 I/O O adx<5> 2 0 0 3 FB1_17 18 I/O O (unused) 0 0 0 5 FB1_18 (b) Signals Used by Logic in Function Block 1: ad<7>.PIN 7: a<2> 12: a<7> 2: ad<6>.PIN 8: a<3> 13: ad<2> 3: ad<5>.PIN 9: a<4> 14: ad<3> 4: ad<4>.PIN 10: a<5> 15: ad<4> 5: a<0> 11: a<6> 16: ale 6: a<1> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs nic_cs_n ....XXXXXXXX............................ 8 8 sramcs_n ..........XX............................ 2 2 sa<4> ...........X..X......................... 2 2 sa<3> ...........X.X.......................... 2 2 sa<2> ...........XX........................... 2 2 adx<6> .X.............X........................ 2 2 adx<7> X..............X........................ 2 2 adx<4> ...X...........X........................ 2 2 adx<5> ..X............X........................ 2 2 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 18/18 Number of signals used by logic mapping into function block: 18 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 39 I/O I (unused) 0 0 0 5 FB2_2 38 I/O I sa<0> 2 0 0 3 FB2_3 36 GTS/I/O O (unused) 0 0 0 5 FB2_4 37 I/O I sa<1> 1 0 0 4 FB2_5 34 GTS/I/O O ad<6> 1 0 0 4 FB2_6 33 GSR/I/O I/O ad<7> 1 0 0 4 FB2_7 32 I/O I/O ad<4> 3 0 0 2 FB2_8 31 I/O I/O ad<5> 1 0 0 4 FB2_9 30 I/O I/O ad<2> 3 0 0 2 FB2_10 29 I/O I/O ad<3> 3 0 0 2 FB2_11 28 I/O I/O ad<0> 3 0 0 2 FB2_12 27 I/O I/O ad<1> 3 0 0 2 FB2_13 23 I/O I/O adx<1> 2 0 0 3 FB2_14 22 I/O O adx<0> 2 0 0 3 FB2_15 21 I/O O adx<3> 2 0 0 3 FB2_16 20 I/O O adx<2> 2 0 0 3 FB2_17 19 I/O O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: ad<4>.PIN 7: a<1> 13: a<7> 2: ad<3>.PIN 8: a<2> 14: ad<0> 3: ad<2>.PIN 9: a<3> 15: ad<1> 4: ad<1>.PIN 10: a<4> 16: ale 5: ad<0>.PIN 11: a<5> 17: rd_n 6: a<0> 12: a<6> 18: wd_n Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs sa<0> ...........XXX.......................... 3 3 sa<1> ............X.X......................... 2 2 ad<6> .....XXXXXXXX...X....................... 9 9 ad<7> .....XXXXXXXX...X....................... 9 9 ad<4> X....XXXXXXXX...XX...................... 11 11 ad<5> .....XXXXXXXX...X....................... 9 9 ad<2> ..X..XXXXXXXX...XX...................... 11 11 ad<3> .X...XXXXXXXX...XX...................... 11 11 ad<0> ....XXXXXXXXX...XX...................... 11 11 ad<1> ...X.XXXXXXXX...XX...................... 11 11 adx<1> ...X...........X........................ 2 2 adx<0> ....X..........X........................ 2 2 adx<3> .X.............X........................ 2 2 adx<2> ..X............X........................ 2 2 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FDCPE_ad0: FDCPE port map (ad_I(0),'0','0',ad_CLR(0),ad_PRE(0)); ad_CLR(0) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT wd_n AND NOT ad(0).PIN); ad_PRE(0) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT wd_n AND ad(0).PIN); ad(0) <= ad_I(0) when ad_OE(0) = '1' else 'Z'; ad_OE(0) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT rd_n); FDCPE_ad1: FDCPE port map (ad_I(1),'0','0',ad_CLR(1),ad_PRE(1)); ad_CLR(1) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT wd_n AND NOT ad(1).PIN); ad_PRE(1) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT wd_n AND ad(1).PIN); ad(1) <= ad_I(1) when ad_OE(1) = '1' else 'Z'; ad_OE(1) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT rd_n); FDCPE_ad2: FDCPE port map (ad_I(2),'0','0',ad_CLR(2),ad_PRE(2)); ad_CLR(2) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT wd_n AND NOT ad(2).PIN); ad_PRE(2) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT wd_n AND ad(2).PIN); ad(2) <= ad_I(2) when ad_OE(2) = '1' else 'Z'; ad_OE(2) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT rd_n); FDCPE_ad3: FDCPE port map (ad_I(3),'0','0',ad_CLR(3),ad_PRE(3)); ad_CLR(3) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT wd_n AND NOT ad(3).PIN); ad_PRE(3) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT wd_n AND ad(3).PIN); ad(3) <= ad_I(3) when ad_OE(3) = '1' else 'Z'; ad_OE(3) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT rd_n); FDCPE_ad4: FDCPE port map (ad_I(4),'0','0',ad_CLR(4),ad_PRE(4)); ad_CLR(4) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT wd_n AND NOT ad(4).PIN); ad_PRE(4) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT wd_n AND ad(4).PIN); ad(4) <= ad_I(4) when ad_OE(4) = '1' else 'Z'; ad_OE(4) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT rd_n); ad_I(5) <= '0'; ad(5) <= ad_I(5) when ad_OE(5) = '1' else 'Z'; ad_OE(5) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT rd_n); ad_I(6) <= '0'; ad(6) <= ad_I(6) when ad_OE(6) = '1' else 'Z'; ad_OE(6) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT rd_n); ad_I(7) <= '0'; ad(7) <= ad_I(7) when ad_OE(7) = '1' else 'Z'; ad_OE(7) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND a(1) AND a(0) AND NOT rd_n); FDCPE_adx0: FDCPE port map (adx(0),'0','0',adx_CLR(0),adx_PRE(0)); adx_CLR(0) <= (ale AND NOT ad(0).PIN); adx_PRE(0) <= (ale AND ad(0).PIN); FDCPE_adx1: FDCPE port map (adx(1),'0','0',adx_CLR(1),adx_PRE(1)); adx_CLR(1) <= (ale AND NOT ad(1).PIN); adx_PRE(1) <= (ale AND ad(1).PIN); FDCPE_adx2: FDCPE port map (adx(2),'0','0',adx_CLR(2),adx_PRE(2)); adx_CLR(2) <= (ale AND NOT ad(2).PIN); adx_PRE(2) <= (ale AND ad(2).PIN); FDCPE_adx3: FDCPE port map (adx(3),'0','0',adx_CLR(3),adx_PRE(3)); adx_CLR(3) <= (ale AND NOT ad(3).PIN); adx_PRE(3) <= (ale AND ad(3).PIN); FDCPE_adx4: FDCPE port map (adx(4),'0','0',adx_CLR(4),adx_PRE(4)); adx_CLR(4) <= (ale AND NOT ad(4).PIN); adx_PRE(4) <= (ale AND ad(4).PIN); FDCPE_adx5: FDCPE port map (adx(5),'0','0',adx_CLR(5),adx_PRE(5)); adx_CLR(5) <= (ale AND NOT ad(5).PIN); adx_PRE(5) <= (ale AND ad(5).PIN); FDCPE_adx6: FDCPE port map (adx(6),'0','0',adx_CLR(6),adx_PRE(6)); adx_CLR(6) <= (ale AND NOT ad(6).PIN); adx_PRE(6) <= (ale AND ad(6).PIN); FDCPE_adx7: FDCPE port map (adx(7),'0','0',adx_CLR(7),adx_PRE(7)); adx_CLR(7) <= (ale AND NOT ad(7).PIN); adx_PRE(7) <= (ale AND ad(7).PIN); nic_cs_n <= NOT ((a(7) AND a(6) AND NOT a(5) AND NOT a(4) AND NOT a(3) AND NOT a(2) AND NOT a(1) AND NOT a(0))); sa(0) <= ((a(7) AND NOT ad(0)) OR (NOT a(7) AND a(6))); sa(1) <= (a(7) AND NOT ad(1)); sa(2) <= (a(7) AND NOT ad(2)); sa(3) <= (a(7) AND NOT ad(3)); sa(4) <= (a(7) AND NOT ad(4)); sramcs_n <= (a(7) AND a(6)); Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9536-5-VQ44 -------------------------------- /44 43 42 41 40 39 38 37 36 35 34 \ | 1 33 | | 2 32 | | 3 31 | | 4 30 | | 5 XC9536-5-VQ44 29 | | 6 28 | | 7 27 | | 8 26 | | 9 25 | | 10 24 | | 11 23 | \ 12 13 14 15 16 17 18 19 20 21 22 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 ale 23 ad<1> 2 nic_cs_n 24 TDO 3 rd_n 25 GND 4 GND 26 VCC 5 wd_n 27 ad<0> 6 sramcs_n 28 ad<3> 7 sa<4> 29 ad<2> 8 sa<3> 30 ad<5> 9 TDI 31 ad<4> 10 TMS 32 ad<7> 11 TCK 33 ad<6> 12 sa<2> 34 sa<1> 13 adx<6> 35 VCC 14 adx<7> 36 sa<0> 15 VCC 37 a<0> 16 adx<4> 38 a<1> 17 GND 39 a<2> 18 adx<5> 40 a<3> 19 adx<2> 41 a<4> 20 adx<3> 42 a<5> 21 adx<0> 43 a<6> 22 adx<1> 44 a<7> Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9536-5-VQ44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : ON Pin Feedback : ON Input Limit : 36 Pterm Limit : 25