Equations

********** Mapped Logic **********
FDCPE_ad0: FDCPE port map (ad_I(0),'0','0',ad_CLR(0),ad_PRE(0));
     ad_CLR(0) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT wd_n AND NOT ad(0).PIN);
     ad_PRE(0) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT wd_n AND ad(0).PIN);
     ad(0) <= ad_I(0) when ad_OE(0) = '1' else 'Z';
     ad_OE(0) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT rd_n);
FDCPE_ad1: FDCPE port map (ad_I(1),'0','0',ad_CLR(1),ad_PRE(1));
     ad_CLR(1) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT wd_n AND NOT ad(1).PIN);
     ad_PRE(1) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT wd_n AND ad(1).PIN);
     ad(1) <= ad_I(1) when ad_OE(1) = '1' else 'Z';
     ad_OE(1) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT rd_n);
FDCPE_ad2: FDCPE port map (ad_I(2),'0','0',ad_CLR(2),ad_PRE(2));
     ad_CLR(2) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT wd_n AND NOT ad(2).PIN);
     ad_PRE(2) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT wd_n AND ad(2).PIN);
     ad(2) <= ad_I(2) when ad_OE(2) = '1' else 'Z';
     ad_OE(2) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT rd_n);
FDCPE_ad3: FDCPE port map (ad_I(3),'0','0',ad_CLR(3),ad_PRE(3));
     ad_CLR(3) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT wd_n AND NOT ad(3).PIN);
     ad_PRE(3) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT wd_n AND ad(3).PIN);
     ad(3) <= ad_I(3) when ad_OE(3) = '1' else 'Z';
     ad_OE(3) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT rd_n);
FDCPE_ad4: FDCPE port map (ad_I(4),'0','0',ad_CLR(4),ad_PRE(4));
     ad_CLR(4) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT wd_n AND NOT ad(4).PIN);
     ad_PRE(4) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT wd_n AND ad(4).PIN);
     ad(4) <= ad_I(4) when ad_OE(4) = '1' else 'Z';
     ad_OE(4) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT rd_n);
ad_I(5) <= '0';
     ad(5) <= ad_I(5) when ad_OE(5) = '1' else 'Z';
     ad_OE(5) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT rd_n);
ad_I(6) <= '0';
     ad(6) <= ad_I(6) when ad_OE(6) = '1' else 'Z';
     ad_OE(6) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT rd_n);
ad_I(7) <= '0';
     ad(7) <= ad_I(7) when ad_OE(7) = '1' else 'Z';
     ad_OE(7) <= (a(7) AND a(6) AND a(5) AND a(4) AND a(3) AND a(2) AND
      a(1) AND a(0) AND NOT rd_n);
FDCPE_adx0: FDCPE port map (adx(0),'0','0',adx_CLR(0),adx_PRE(0));
     adx_CLR(0) <= (ale AND NOT ad(0).PIN);
     adx_PRE(0) <= (ale AND ad(0).PIN);
FDCPE_adx1: FDCPE port map (adx(1),'0','0',adx_CLR(1),adx_PRE(1));
     adx_CLR(1) <= (ale AND NOT ad(1).PIN);
     adx_PRE(1) <= (ale AND ad(1).PIN);
FDCPE_adx2: FDCPE port map (adx(2),'0','0',adx_CLR(2),adx_PRE(2));
     adx_CLR(2) <= (ale AND NOT ad(2).PIN);
     adx_PRE(2) <= (ale AND ad(2).PIN);
FDCPE_adx3: FDCPE port map (adx(3),'0','0',adx_CLR(3),adx_PRE(3));
     adx_CLR(3) <= (ale AND NOT ad(3).PIN);
     adx_PRE(3) <= (ale AND ad(3).PIN);
FDCPE_adx4: FDCPE port map (adx(4),'0','0',adx_CLR(4),adx_PRE(4));
     adx_CLR(4) <= (ale AND NOT ad(4).PIN);
     adx_PRE(4) <= (ale AND ad(4).PIN);
FDCPE_adx5: FDCPE port map (adx(5),'0','0',adx_CLR(5),adx_PRE(5));
     adx_CLR(5) <= (ale AND NOT ad(5).PIN);
     adx_PRE(5) <= (ale AND ad(5).PIN);
FDCPE_adx6: FDCPE port map (adx(6),'0','0',adx_CLR(6),adx_PRE(6));
     adx_CLR(6) <= (ale AND NOT ad(6).PIN);
     adx_PRE(6) <= (ale AND ad(6).PIN);
FDCPE_adx7: FDCPE port map (adx(7),'0','0',adx_CLR(7),adx_PRE(7));
     adx_CLR(7) <= (ale AND NOT ad(7).PIN);
     adx_PRE(7) <= (ale AND ad(7).PIN);
nic_cs_n <= NOT ((a(7) AND a(6) AND NOT a(5) AND NOT a(4) AND NOT a(3) AND NOT a(2) AND
      NOT a(1) AND NOT a(0)));
sa(0) <= ((a(7) AND NOT ad(0))
      OR (NOT a(7) AND a(6)));
sa(1) <= (a(7) AND NOT ad(1));
sa(2) <= (a(7) AND NOT ad(2));
sa(3) <= (a(7) AND NOT ad(3));
sa(4) <= (a(7) AND NOT ad(4));
sramcs_n <= (a(7) AND a(6));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE);
      FTCPE (Q,D,C,CLR,PRE);
      LDCP (Q,D,G,CLR,PRE);